/*
 * iomap.h
 *
 *  Created on: 6 juil. 2009
 *      Author: sylvain
 */

#ifndef APCI3200_IOMAP_H_
#define APCI3200_IOMAP_H_

/* A APCI3200 board can contains up to 4 acquisition modules.
 * The actual number of module is programmed in the EEPROM of the board.
 *
 * Each module provides the same I/O mapping, described below, with a offset of (64*i)
 * where i is the module index.
 *
 * A channel has 4 channels in single mode and 2 in differencial.
 */

/* channel configuration
 *
 * - write: Write the channel configuration
 * 0..2 : gain  Define the gain of this channel
 *        000000 : First Gain available
 *        000001 : Second Gain available
 * 6 : U/B
 *        0 : Bipolar
 *        1 : Unipolar
 * 7 : D/S  Define the input mode: Single-ended or differential.
 *        0 : Single-ended
 *        1 : Differential
 * 8..11 : OFFSET Define the offset-correction DAC
 *
 * - read
 * 6 : U/B
 * 7 : D/S
 * 8..11 : offset
 * ?? : AC/DC
 */
#define APCI3200_REG_CHANNEL_CONFIG (0)

/* acquisition configuration
 *
 * - write
 * 0..1 : MUX Define the index of channel to sequence/SCAN
 *
 * 10 : CJC
 *        0 : CJC Conversion not selected
 *        1 : CJC Conversion selected
 *
 * 11 : Burn out
 *        1 : Enable burn out current sources
 *        0 : Disable burn out current sources
 *
 * 12 : short-circuit
 *        1 : Enable short-circuit test
 *        0 : Disable short-circuit test
 *
 * 13 : scan
 *        0 : No SCAN selected
 *        1 : SCAN Mode selected
 *
 * 18..20 : delay mode
 *        000 : Delay is used between 2 cycle of acquisition .By start of the acquisition (software or trigger ext), the
 *            acquisition is started and the delay is activated after this acquisition cycle.
 *        001 : Delay is used between 2 cycle of acquisition but by start of the acquisition (software or trigger ext), the
 *             acquisition is do after the delay
 *
 * - read
 * 0..1: MUX
 * 10 : CJC
 * 11 : burn-out
 * 12 : short
 * 13 : scan
 *
 */
#define APCI3200_REG_ACQUISITION_CONFIG (4)

/* scan configuration
 *
 * - write
 * 16..17 : sequence/scan mode
 *        00 : Do the sequence/SCAN or DMA cycle 1 time
 *        01 : Do the sequence/SCAN or DMA cycle x time (x is the value of the counter).
 *        10 : Do always the sequence/SCAN or DMA cycle (continuous)
 *
 * 18 : Delay
 * 0 : Disable the delay
 * 1 : Enable the delay
 *
 * 19 : Start / Stop
 *      0 : Stop the acquisition
 *      1 : Start the acquisition. It’s set automatically to 0 after 1 cycle
 *          stopped and SCAN Mode = 00 or after the last cycle stopped
 *          and SCAN Mode = 01
 *
 * 20 : IRQ
 *      0 : Disable the interrupt
 *      1 : Enable the interrupt

 * 24..31 : Trigger
 *      Configure the external trigger.
 *      Bit 0 : 1 : enable the external trigger
 *              0 : disable the external trigger
 *      Bit 1,2 : define the active front
 *           01 : ? front
 *           10 : ? front
 *           11 : Both front
 *      Bit 3,4,5,6 : Define the trigger mode
 *           0000 : External trigger start a sequence/SCAN
 *           0001 : External trigger start a DMA Cycles
 *
 * - read
 * 16..17 : sequence/scan mode
 * 18 : delay
 * 19 : start
 * 20 : IRQ
 * 24..31 : Trigger
 *
 */
#define APCI3200_REG_ACQUISITION_CONTROL (8)

/* auto-calibration/ready bit/buffer
 *
 * - write
 * 17..18: auto-calibration
 *      01 : : Offset calibration on course. The Hardware must read the offset calibration register and
 *      save its value. When the value has been read the bit is reset.
 *      10 : : Gain calibration on course. The Hardware must read the gain calibration register and
 *      save its value. When the value has been read the bit is reset.
 *      00 : Gain and offset calibration OK. The Hardware use the saved offset and gain value to do the
 *      calibration

 * 20 : buffer
 *
 * - read
 * 17..18 : auto-calibration
 * 19 : ready bit : synchronises the outport access on the board.
 *      1 : Ready bit set -> Outport can be done
 *      0 : Ready bit not set -> Outport cannot be done.
 * 20 : buffer
 *      0 : Disable the input buffer
 *      1 : Enable the input buffer
 */
#define APCI3200_REG_READYBIT (12)
#define APCI3200_REG_AUTOCALIBRATION (12)

/* EOS-IRQ (End Of Sequence IRQ)
 *
 * 1 : EOS
 *      0 : No end of sequence/SCAN interrupt occur
 *      1 : End of sequence/SCAN interrupt occur. It’s reset after a dummy write of this address
 */
#define APCI3200_REG_EOSIRQ (16)

/* EOS
 * 0 : EOS flag
 *      0 : End of sequence/SCAN not occur
 *      1 : End of sequence/SCAN occur.
 *      This bit is reset after reading the value from SCAN
 */
#define APCI3200_REG_EOS (20)

/* channel ID
 *
 * - read
 * 0..31 : channel ID
 *      Channel number / Number of acquisition:
 *            Returns the channel number if only 1 acquisition occur.
 *            Return the number of channels if more acquisitions occur

 */
#define APCI3200_REG_CHANNEL_ID (24)

/* channel value
 *
 * - read
 * 0..31 : channel value
 */
#define APCI3200_REG_CHANNEL_VALUE (28)

/* time value
 *
 * - write
 * 0..31: reload time value
 *
 * - read
 * 0..31: reload time value
 */
#define APCI3200_REG_CONVERSION_VALUE (32)

/* time base
 * - write
 * 0..31: reload time base
 *        X00 : ns or MHz
 *        X01 : µs or kHz
 *        X10 : ms or Hz
 *        X11 : s or mHz
 * - read
 * 0..31: reload time base
 */
#define APCI3200_REG_CONVERSION_BASE (36)

/* delay time value
 *
 * - write
 * 0..31: reload delay time value
 *
 * - read
 * 0..31: delay time value
 */
#define APCI3200_REG_DELAY_VALUE (40)

/* delay time base
 *
 * - write
 * 0..31: reload delay time base
 *        X00 : ns or MHz
 *        X01 : µs or kHz
 *        X10 : ms or Hz
 *        X11 : s or mHz
 *
 * - read
 * 0..31: reload delay time base
 */
#define APCI3200_REG_DELAY_BASE (44)

#endif /* APCI3200_IOMAP_H_ */
