#ifndef __APCI3701_IOMAP_H__
#define __APCI3701_IOMAP_H__

//---------------------------------------------------------------

/**@def ANALOG_SEQUENCE_START_STOP_BITMASK
 * This mask can be used to start or stop an acquisition.
 */
#define ANALOG_SEQUENCE_START_STOP_BITMASK	0x00080000

/**@def ANALOG_SEQUENCE_MODE_CONTINUOUS
 * Acquisition in continuous mode.
 */
#define ANALOG_SEQUENCE_MODE_CONTINUOUS		0x00010000

/**@def  ANALOG_SEQUENCE_START_BITMASK
 * Analog input sequence begin at (start) channel index - mask 
 */
 
#define ANALOG_SEQUENCE_START_BITMASK		0x0000000F

/**@def ANALOG_SEQUENCE_STOP_BITMASK 
 * Analog input sequence terminate (stop) at channel index - mask 
 */
#define ANALOG_SEQUENCE_STOP_BITMASK		0x00000F00

/**@def APCI3701_REG_DIGITAL_INPUT
 * Offset to read digital input value in BAR2
 */
#define APCI3701_REG_DIGITAL_INPUT				0x8

/**@def APCI3701_REG_DIGITAL_OUTPUT
 * Offset to write digital output value in BAR2
 */
#define APCI3701_REG_DIGITAL_OUTPUT				0xC

/**@def APCI3701_CHANNEL_NUMBER
 * Offset to read/write channel number BAR3
 */

#define APCI3701_REG_CHANNEL_NUMBER (0)

/**@def APCI3701_REG_SEQUENCE_INDEX
 * Offset to read/write sequnce index BAR3
 */

#define APCI3701_REG_SEQUENCE_INDEX (4)

/**@def APCI3701_SEQUENCE_INDEX
 * Offset to read/write sequence index 
 * 
 * BAR3 -read/write
 * 
Address + 8 :
D0-D7 :	Start Sequence
		Set the start index for the sequence array conversion
D8-D15 :	Stop Sequence
		Set the stop index for the sequence array / SCAN conversion
D16-D17 :	Sequence Mode : define the acquisition sequence
		00 : 	Do the sequence or DMA cycle x time (x is the value of the counter).
		01 : 	Do always the sequence or DMA cycle (continuous)
D18 :	Delay Enable
		0 :	Disable
		1 :	Enable
D19 :	Start Enable
		0 : 	Stop the acquisition in continuous mode
		1 : 	Start enable. It?s set automatically to 0 after 1 cycle in single mode or after the last cycle in x sequence mode
D20 :	IRQ
		0 :	IRQ disable
		1 :	IRQ enable
D21 :	DMA (32-Bit)
		0 :	DMA disable
		1 :	DMA enable (Enables the FIFO IRQ, and the DMA Counter IRQ)
It disables the EOS. 
 */

#define APCI3701_REG_SEQUENCE_CONTROL (8)


/** APCI3701_REG_CLEAR_INDEX
D16 :		Clear Index : initialise the sequence Index and the FIFO addresses. When the acquisition is stopped and restarted 
0 :	The acquisition carry on the sequence.
1 :	Clear Index is on 1, the index of the sequence is initialised, the acquisition begin on the first element of the sequence, and the FIFO address is initialised. The DMA Counter is initialised.
*/
#define APCI3701_REG_CLEAR_INDEX (12)

/**@def APCI3701_REG_ANALOG_INPUT_IRQ_STATUS
 * 
 * BAR 3 - read/write
 *
D0 :	Counter IRQ : Sequence Counter Overflow
0 : 	No counter interrupt occured
1 : 	Counter interrupt occured. It is reset after a dummy 1 write on this address on this bit.
D1 :	EOS IRQ : EOC (Single Read) or EOS (Sequence Read)
0 : 	No end of sequence interrupt occured
1 : 	End of sequence interrupt occured. It iss reset after a dummy 1 write on this address on this bit.
D2 :	DMA IRQ : PCI9054 DMA IRQ
0 : 	No DMA interrupt occured
1 : 	DMA interrupt occured. It is reset after a dummy ?1? write on this address on this bit.
D4 :	DMA Counter IRQ : 
0 : 	No DMA Counter interrupt occured
1 : 	DMA Counter Overflow interrupt occured. It is reset after a dummy 1 write on this address on this bit.
D5 :	FIFO IRQ : PLD FIFO Over-Run
0 : 	No FIFO interrupt occured
1 : 	FIFO Overflow interrupt occured. It is reset after a dummy 1 write on this address on this bit.
 * 
 */

#define APCI3701_REG_ANALOG_INPUT_IRQ_STATUS (16)

/**@def APCI3701_REG_DIVISION_FACTOR
 * Division factor
 */

#define APCI3701_REG_ANALOG_INPUT_EOS_STATUS (20)
/*
 * Address of the EOS bit
 */

#define APCI3701_ANALOG_INPUT_CHANNEL_VALUE (28)
/*
 * Address of the value of the channel
 */


#define APCI3701_REG_DIVISION_FACTOR (32)

/**@def APCI3701_REG_SEQUENCE_COUNTER
 * Sequence counter (incremented each time a sequence is finished) BAR3
 */

#define APCI3701_REG_SEQUENCE_COUNTER (48)

#define APCI3701_REG_SEQUENCE_COUNTER_M (52)

/** APCI3701_REG_DMA_TRANSFER_SIZE
BAR 3
D0-D31 :	DMA Transfer Size (Word).
D0-D31 :	0x00000000 : Continuous Mode : Die Software muss den DMA Transfer stoppen (Abort)
	0xXXXXXXXX : Der DMA Transfer lauft bis zum DMA Transfer Size Wert, dann wird er gestoppt.
*/
#define APCI3701_REG_DMA_TRANSFER_SIZE (56)

/**
Address + 64 :
D0-D6		Hardware trigger initialisation :
		D0 :	Trigger enable
			0 : 	disable the external trigger
					1 :	enable the external trigger
				D1-D2	Trigger front		
		  			01 : 	? front
		  			10 : 	? front
		  			11 : 	Both fronts
				D3-D6	Trigger mode
		0000 : 	One shot Trigger (wie der Software Start)
		0010 : 	Each X trigger starts Y sequences
D7 		Hard Trg Status:
				0 : No hardware trigger occur
			  	1 : Hardware trigger occur. 
				     It is set to 1 after Trigger count value equal Ext Trigger count value
	D8		Hard Trg State: 
				0 : Hardware trigger input is low 
			  	1 : Hardware trigger input is high

D16-D31 :	Return the number that of trigger event that occur.
*/
#define APCI3701_REG_HARDWARE_TRIGGER (64)

/**
 * 
 * Address + 96 to Address + 156 :

D15-D24:	Taster type	Determine the taster type:
0000000 : Calibration
	0000001 : Secondary diagnotic configuration selection
				0000010 : Kn�bel
				0000011 : Schlumberger AGH 1
				0000100 : TESA GT21/22
				0000101 : TESA GT21HP/22HP
				0000110 : ATI AXH1.0
				0000111 : Mahr 1300
				0001000 : Mahr 1301/1303
				0001001 : Klingelnberg Sagamo
				0001010 : Solartron AX1.0S
				0001011 : Mahrposs
				0001100 : Peter&Hirt T109/110
				0001101 : RDP D5/200AG
*/

#define APCI3701_REG_TRANSDUCER_CONFIG_BASE (96)

/**@def APCI3701_REG_AUTOREFRESH_VALUES
 * Area to read values in autorefresh mode 
 */

#define APCI3701_REG_AUTOREFRESH_VALUES_BASE (192)


/*
 * Diagnostic IO MAP
 */
#define APCI3701_DIAGNOSTIC_COMMAND 84 // + GET_BAR3() MEM MAP

#define APCI3701_DIAGNOSTIC_STATUS 88 // + GET_BAR3() MEM MAP

#define APCI3701_DIAGNOSTIC_SHORT_CIRCUIT_INTERRUPT 92 // + GET_BAR3() MEM MAP

#define APCI3701_DIAGNOSTIC_INTERRUPTION_SHORT_CIRCUIT 0x2




#endif // __APCI3701_IOMAP_H__
