#ifndef __APCIE1532_IOMAP_H__
#define __APCIE1532_IOMAP_H__

/* DIGITAL INPUT (BAR 3) */ 

/* read-only register 
 * D0: input 0
 * Dn: input n
 */
#define APCIE1532_DIGITAL_INPUT_REG							(0x00)

/* modus 1 configuration for channel 1 to 15
 * 
 * read,write
 * 
 * width: 32 bits
 * 
 * D1: modus 1 for channel 1
 * D2: modus 1 for channel 2
 * D3: modus 1 for channel 3
 * D4: modus 1 for channel 4
 * D5: modus 1 for channel 5
 * D6: modus 1 for channel 6
 * D7: modus 1 for channel 7
 * D8: modus 1 for channel 8
 * D9: modus 1 for channel 9
 * D10: modus 1 for channel 10
 * D11: modus 1 for channel 11
 * D12: modus 1 for channel 12
 * D13: modus 1 for channel 13
 * D14: modus 1 for channel 14
 * D15: modus 1 for channel 15
 *  
 * */
#define APCIE1532_DIGITAL_INPUT_INTERRUPT_MODUS1_REG			(0x04) /**< control diagnostic interrupts  */

/* modus 2 configuration for channel 1 to 15
 * read,write
 * 
 * width: 32 bits
 * 
 * D1: modus 2 for channel 1
 * D2: modus 2 for channel 2
 * D3: modus 2 for channel 3
 * D4: modus 2 for channel 4
 * D5: modus 2 for channel 5
 * D6: modus 2 for channel 6
 * D7: modus 2 for channel 7
 * D8: modus 2 for channel 8
 * D9: modus 2 for channel 9
 * D10: modus 2 for channel 10
 * D11: modus 2 for channel 11
 * D12: modus 2 for channel 12
 * D13: modus 2 for channel 13
 * D14: modus 2 for channel 14
 * D15: modus 2 for channel 15
 *
 */
#define APCIE1532_DIGITAL_INPUT_INTERRUPT_MODUS2_REG			(0x08) 


#define APCIE1532_DIGITAL_INPUT_INTERRUPT_STATUS_REG			(0xC)


/* global interrupt logic 
 * read,write
 * 
 * D1 
 * 0: OR 
 * 1: AND
 * 
 * D2
 * 0: disable IRQ
 * 1: enable IRQ

The behaviour of the interrupt for each input is the combination of :
* the bit modus 1 for this channel, 
* the bit modus 2 for this channel 
* and the global interrupt logic bit
 
      +-----------+-----------------+-----------------+-----------------+------------------------+
      | MODUS 1   |        0        |        1        |        0        |            1           |
      +-----------+-----------------+-----------------+-----------------+------------------------+
      | MODUS 2   |        0        |        0        |        1        |            1           |
      +-----------+-----------------+-----------------+-----------------+------------------------+
      | INTERRUPT |                 |                 |                 |                        |
      | OR LOGIC  |     DISABLE     |   RISING EDGE   |   FALLING EDGE  |       BOTH EDGES       |
      +-----------+-----------------+-----------------+-----------------+------------------------+
      | INTERRUPT |     DISABLE     |   HIGH STATUS   |   LOW STATUS    | LOW AND HIGH STATUS    |
      | AND LOGIC |                 |                 |                 |                        |
      +-----------+-----------------+-----------------+-----------------+------------------------+
*/ 

#define APCIE1532_DIGITAL_INPUT_INTERRUPT_LOGIC_REG			(0x10)

/* DIGITAL OUTPUT OFFSET DEFINE */
#define APCIE1532_DIGITAL_OUTPUT_REG							(0x20)	

/* COUNTERS (BAR 3) */

/* COMMON REGISTERS TO TIMER/COUNTER/WATCHDOG ( hence TWC) */
#define APCIE1532_TIMERWATCHDOG_OFFSET 				(0x40)

#define APCIE1532_COUNTER_OFFSET					(0x80)

/* VALUE REGISTER
 * 
 * D0-D32: current value of the TCW
 * 
 */
#define APCIE1532_TCW_VALUE_REG								(0)

/* RELOAD VALUE REGISTER
 * 
 * D0-D32: reload value of the TCW
 * 
 */
#define APCIE1532_TCW_RELOAD_VALUE_REG						(0x04)

/* TIME BASE FOR TIMER/WATCHDOG
				0 : micro seconds
				1 : milliseconds
				2 : seconds
*/
#define APCIE1532_TCW_TIME_BASE_REG							(0x08)

/* Timer/counter/watchdog control register
 * 
 *  
 * 
	D0: Enable/Disable
	D1: Enable/Disable IRQ
	D2: E/D Warning ( Watchdog only  )
	D3: E/D Reset ( Watchdog only )
	D4: E/D Timer ( Watchdog only )
	D5-D6: external trigger
				00 : Extern trigger disabled (Read/write)
				01 : Extern trigger enabled (Low level)
				10 : Extern trigger enabled (High level) 
	D7-D8: external gate
                00 : Extern gate disabled (Read/write)
				01 : Extern gate enabled (Low level)
				10 : Extern gate enabled (High level)
	D9: (write) : sofwtare trigger
		(read) external trigger state:
   				0 : Extern trigger not activate (Read)
				1 : Extern trigger activate
	D10: clear counter (Only if extern clock enabled)
	D11-D12: output
				00 : Output signal not used
				01 : Output signal activated
				10 : Output signal activated and inverted
	D13-D15: timer mode 
				000 : Mode 0 initialised
				001 : Mode 1 initialised
				010 : Mode 2 initialised
				011 : Mode 3 initialised
				100 : Mode 4 initialised
				101 : Mode 5 initialised
	D16-D17: external clock
				00 : Disable extern Timer/Counter clock
				01 : Enable extern Timer/Counter clock. Count falling edge
				10 : Enable extern Timer/Counter clock. Count rising edge
				11 : Enable extern Timer/Counter clock. Count falling /rising edge
	D18: Up/Down
				Counter direction selection
				0 : Down
				1 : Up
	D19: E/D Counter
				1 : Used for counter (Read/write)
				0 : Used for watchdog if E/D timer not set
	D20: Cascade
				Output from /Timer/Counter/Watchdog is cascaded to the next
	
	D21: external clock status
				0 : Extern clock is set to 0
				1 : Extern clock is set to 1		
	D22: output status
				0 : Output is set to 0
				1 : Output is set to 1
	D23: Reset-Relay-Mode
				0: Reset relay is set when Watchdog has run down.
				1: Reset relay is reset when Watchdog has run down.
				
	Note: the fields above aren't present on all boards and for all TCW. refer to the actual iomapping.
*/

#define APCIE1532_TCW_CONTROL_REG							(0x0C)

/* STATUS REGISTER
 * D0: Overflow (read)
 * 				0 : No overflow occurs
				1 : Overflow occurs
 * D1: status software trigger (read)
 * 				0 : No software trigger occur (Read)
				1 : Software trigger occur
 * D2: Status external trigger
 * 				0 : No extern trigger occur (Read)
 *				1 : Extern trigger occur (Read)
 * D3:Status software clear
 * 				0 : No software clear occur (Read)
				1 : Software clear occur
 * D4: ready bit 
 */
#define APCIE1532_TCW_STATUS_REG								(0x10)

/* IRQ STATUS REGISTER
 * 
 * D0: (read)
 * 				0 : No interrupt occur
				1 : Interrupt occur
 * 
 */
#define APCIE1532_TCW_IRQ_REG								(0x14)


#endif // __APCIE1532_IOMAP_H__
